Fuse cells are widely used in ICs in order to make the ICs tunable. For example, after an IC designed by an IC supplier is manufactured it may happen that, due to the manufacturing process, the performance of the ICs is not what was intended. In this case, the performance of the ICs can be modified by cutting a selection of the fuses before the ICs are supplied to customers. As an example, fuse cells can be used to store addressing information of defective memory cells in an array for redundancy applications.
When the IC supplier contemplates cutting the fuses of an IC it may wish to check that the resulting performance of the IC will be what is desired. For that reason, it is known to provide circuitry on the IC for simulating the cut and uncut fuse states and which is controllable using control signals. Control signals are applied to the circuit to cause this circuitry to simulate the proposed cutting of fuses, and the performance of the IC is then investigated.
FIG. 1 shows a conventional fuse cell 101 comprising a pull-up circuit. As shown, a fuse 110 is coupled between the pull-up (logic 1 or high) power source and ground (logic 0 or low). Coupled between the fuse and the pull-up power source is a fuse cell output terminal 160. The output signal of the fuse cell indicates the state of the fuse (cut or uncut). A cut fuse produces a logic 1 output while an uncut fuse produces a logic 0 output.
When the fuse is not cut, the pull-up power source is coupled to ground via the fuse 110. Thus, even when the fuse is in a static state, power dissipates through the fuse which increases the IC's power consumption. The increased power consumption is undesirable, particularly for low power applications.
An additional desideratum for a fuse cell of an integrated circuit is that when it is in the cut state the voltage across it is low. In this case, deep sub-micron technologies provide leakage paths across cut (or “blown”) fuses due to corrosion and applied electrical voltage bias. For this reason, it is a design requirement of certain deep sub-micron technologies (e.g. ones having 180 nm or 130 nm lithographic resolution) that the bias across the blown fuse links be less than 0.1V, this being the maximum voltage allowed to prevent leakage path formation.
When a fuse cell is implemented using the traditional pull-up circuit as described above, the requirement for a low voltage bias in the cut state would have to be implemented with additional circuitry to minimise or eliminate the static power distribution through the uncut fuse. The 0.1V bias requirement means that the additional circuitry is required to identify the cut fuse state, latch and store the fuse state and then isolate the fuse element so that no bias exceeding 0.1V is present across the cut fuse. This would increase the complexity and area of each fuse cell. In applications where many fuses are needed there can be a considerable area penalty.
As evidenced from the above discussion, it is desirable to provide an improved fuse cell with reduced or no static power dissipation, and preferably with a low (or zero) bias across the fuse cell in the case that the fuse cell is cut.